I'll now provide an overview of the addressing, since that's why most of us are here.
There is a stack of information on the SPI protocol so it isn't necessary to cover it in detail here. Just to recap though, the SPI protocol consists of 8 serial bits per command followed by the 8 bit data byte. For a write instruction, the first 3 bits is the instruction, the next 5 is the address to write to and the next 8 bits is the data. In this case the read instruction can be ignored since there is no SPO connection to the processor.
Data appearing at the inputs of the 74HC245D is buffered, which increases the fan-out of the logic gates while reducing the loading on the processor. Notice that the CLK and SCLK inputs are each sent to two buffer inputs, which also provides a conditioned signal to the next board in the chain.
The OE signal is inverted to /OE since that is required for correct operation of the 3 to 8 line decoder, 74HC138. It is again inverted back to OE, which ensures that the next board will operate correctly.
Signals A and B are fed directly to the next board in the chain where they will be buffered again. They are also fed to the row selector, pins 1 and 2 of the 74HC138. With A3 tied low this device becomes a 2 to 4 line decoder where each output is mutually exclusive. In other words, only one line can be active at a time. Valid inputs are 0x00, 0x01, 0x10 AND 0x11 and each combination will select (power) a pair of LED chains via the attached 4953s (Dual P-Channel MOSFETs). The resulting selection is any one of (OUT1 and OUT3) or (OUT2 and OUT4) or (OUT5 and OUT7) or (OUT6 and OUT8).
Now comes the interesting stuff...
The 74HC595 is an 8 bit shift register allowing the selection of 16 outputs (in this case LEDs).
- Vcc - Up to 6V, Usually 3.3 / 5v
- Q0 to Q7 - Shift Register Outputs.
- DS - (Serial Input) for the next pin that gets shifted in.
- STCP [SRCLK] (Serial Clock) When this pin is pulled high, it will shift the register.
- SHCP [RCLK] (Register Clock) Needs to be pulled high to set the output to the new shift register values, This must be pulled high directly after SRCLK has gone LOW again.
- /OE (Output Enable) This pin enables the output when tied to GND, & disabled when HIGH.
- /MR (Reset) This active low input resets the device.
OE and MR need not be considered from a programming perspective since both pins are preset in hardware.
The 595 is cascadable simply by joining the D7s output on pin 9 of one device to pin 14 of the next. The "R" input is fed pin 14 of 74HC595-1 and its output D7s (Dout in the schematic) is fed to pin 14 of the next stage. Cascading these devices is only limited only by the processing time available and indeed pin 9 of 74HC595-16 is fed to the "R" input of the next board for that purpose.
As is typical of shift registers, the output is active high, as you would expect. However the 595s are sinking current, which means you must supply the inverse of what you actually want and it will operate in the correct sense.
And that's just about all there is to it, hardware wise.
If anyone would like more detail just ask.